SH7205 Datasheet, PDF (289/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
Table 9.8 Cache Operations
Cache
Hit/
CPU Cycle Miss
Write-Back Mode/
Write Through U
Mode
Bit
External Memory
Accession
Cache Contents
Instruction Instruction Hit

cache
fetch
 Not generated
Not renewed
Miss 
 Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Operand
cache
Prefetch/ Hit
read
Either mode is
available
x Not generated
Not renewed
Miss
Write-through
mode
 Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
Write-back mode 0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle
1 Cache renewal cycle is
Renewed to new values by
generated. Then write-back cache renewal cycle
cycle in write-back buffer is
generated.
Write
Hit
Write-through
 Write cycle CPU issues is Renewed to new values by write
mode
generated.
cycle the CPU issues
Write-back mode x Not generated
Renewed to new values by write
cycle the CPU issues
Miss
Write-through
mode
 Write cycle CPU issues is
generated.
Not renewed*
Write-back mode 0
Cache renewal cycle is
generated
Renewed to new values by
cache renewal cycle.
Subsequently renewed again to
new values in write cycle CPU
issues.
1 Cache renewal cycle is
generated. Then write-back
cycle in write-back buffer is
generated.
[Legend]
x:
Don't care.
Note: Cache renewal cycle: 16-byte read access
Write-back cycle in write-back buffer: 16-byte write access
∗ Neither LRU renewed. LRU is renewed in all other cases.
Renewed to new values by
cache renewal cycle.
Subsequently renewed again to
new values in write cycle CPU
issues.
Rev. 1.00 Mar. 25, 2008 Page 257 of 1868
REJ09B0372-0100