SH7205 Datasheet, PDF (1555/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 I/O Ports
28.2.11 Port F Data Register L (PFDRL)
PFDRL is a 16-bit readable/writable register that stores port F data. The PF4DR to PF0DR bits
correspond to the PF4 to PF0 pins, respectively.
When a pin function is general output, if a value is written to PFDRL, that value is output from the
pin, and if PFDRL is read, the register value is returned regardless of the pin state.
When a pin function is general input, if PFDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PFDRL, although that value is written into PFDRL, it
does not affect the pin state. Table 28.7 summarizes PFDRL read/write operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
PF4 PF3 PF2 PF1 PF0
DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 5 —
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
4
PF4DR 0
R/W See table 28.7.
3
PF3DR 0
R/W
2
PF2DR 0
R/W
1
PF1DR 0
R/W
0
PF0DR 0
R/W
Rev. 1.00 Mar. 25, 2008 Page 1523 of 1868
REJ09B0372-0100