SH7205 Datasheet, PDF (313/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10 to 8 CSPRWAIT 111
[2:0]
R/W Page Read Cycle Wait Select
These bits specify the number of wait states to be inserted
into the second and subsequent page read cycles. This
setting is valid when the page read access enable bit
(PRENB) is set to 1.
000: 0 wait states
:
111: 7 wait states
7 to 3 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
2 to 0
CSPWWAIT 111
[2:0]
R/W Page Write Cycle Wait Select
These bits specify the number of wait states to be inserted
into the second and subsequent page write cycles. This
setting is valid when the page write access enable bit
(PWENB) is set to 1.
000: 0 wait states
:
111: 7 wait states
Notes: 1. Make sure the page read and page write cycle wait select (CSPRWAIT and
CSPWWAIT) settings are within the range defined by the read and write cycle wait
select (CSRWAIT and CSWWAIT) settings. Select each number of wait states
according to the configuration of your system.
2. Writing to the CSn wait control register 1 (CS1WCNTn) must be done while the CSC for
the corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) is allowed
for writing to the register without disabling the CSC (EXENB = 1). To write to
CS1WCNT0 with CSC enabled, satisfy all of the following conditions:
• Stop the DMAC.
• Keep the CPU other than the one that is going to rewrite the register from accessing
CS0 (including access for instruction fetch). For example, if CPU0 is going to rewrite
the register, make CPU1 stay looping by a program copied to on-chip memory, or put
CPU1 in a sleep state.
• Do not perform data write access to CS0 after a reset is released but before the
register is rewritten.
Rev. 1.00 Mar. 25, 2008 Page 281 of 1868
REJ09B0372-0100