SH7205 Datasheet, PDF (191/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
Section 7 Interrupt Controller (INTC)
The interrupt controller (INTC) identifies the priorities of interrupt sources and controls interrupt
requests to the CPU. The INTC has registers used to set interrupt priorities; interrupt requests are
processed according to the priorities set in these registers by the user.
7.1 Features
• 16 levels of interrupt priority can be set.
By setting 19 interrupt priority registers, the priorities of IRQ interrupts, PINT interrupts, and
on-chip peripheral module interrupts can be selected from 16 levels for individual request
sources.
• NMI noise canceller function
An NMI input-level bit indicates the NMI pin state. The pin state can be checked by reading
this bit in the interrupt exception service routine, and this LSI can be used for the noise
canceller function.
• Register banks
This LSI has register banks that enable register contents to be saved and restoration processing
to be performed at high speed for the interrupt processing.
• Inter-processor interrupts
By configuring the inter-processor interrupt control registers, inter-processor interrupts can be
generated with programmed priority levels of 15 to 8.
Rev. 1.00 Mar. 25, 2008 Page 159 of 1868
REJ09B0372-0100