SH7205 Datasheet, PDF (463/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Request Source
Transfer
Transfer Source Destination
IIC3_0 transmission No restriction
ICDRT_0
IIC3_1 transmission
ICDRT_1
IIC3_2 transmission
ICDRT_2
IIC3_3 transmission
ICDRT_3
SCIF_0 reception
SCFRDR_0
No restriction
SCIF_1 reception
SCFRDR_1
SCIF_2 reception
SCFRDR_2
SCIF_3 reception
SCFRDR_3
SCIF_4 reception
SCFRDR_4
SCIF_5 reception
SCFRDR_5
SCIF_0 transmission No restriction
SDFTDR_0
SCIF_1 transmission
SDFTDR_1
SCIF_2 transmission
SDFTDR_2
SCIF_3 transmission
SDFTDR_3
SCIF_4 transmission
SDFTDR_4
SCIF_5 transmission
SDFTDR_5
SSIF_0
Reception:
transmission/reception SSIFDR_n
SSIF_1
(n = channel
transmission/reception ^number)
SSIF_2
Transmission:
transmission/reception ^{No restriction}
Reception:
No restriction
Transmission:
SSIFDR_n
(n = channel
number)
SSIF_3
transmission/reception
SSIF_4
transmission/reception
SSIF_5
transmission/reception
SSU_0 reception
SSRDR0_0 to
SSRDR3_0
No restriction
SSU_1 reception
SSRDR0_1 to
SSRDR3_1
Operand
Transfer Piepelined
Size
Data Size Condition Transfer
(OPSEL) (SZSEL) (DSEL)*¹ (MDSEL)
1
8
Unit
Not
available
1
8
Unit
Not
available
1
8
Unit
Not
available
1, 2, 4 32
Unit
Not
available
1
8, 16
Unit
Not
available
Rev. 1.00 Mar. 25, 2008 Page 431 of 1868
REJ09B0372-0100