SH7205 Datasheet, PDF (1188/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.10 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)
CFIFOSEL, D0FIFOSEL and D1FIFOSEL are registers that select the pipes to be assigned to the
FIFO ports, and control access to the corresponding ports.
The same pipe should not be specified in the CURPIPE bits of CFIFOSEL, D0FIFOSEL and
D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no
pipe is selected.
The pipe number should not be changed while the DMA transfer is enabled.
These registers are initialized by a power-on reset.
(1) CFIFOSEL
Bit: 15 14 13
RCNT REW —
Initial value: 0
0
-
R/W: R/W R/W* R
12 11 10 9
8
7
—
MBW[1:0]
— BIGEND —
-
0
0
-
0
-
R R/W R/W R R/W R
6
5
4
3
2
1
0
— ISEL —
CURPIPE[3:0]
-
0
-
0
0
0
0
R R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
RCNT
0
R/W Read Count Mode
Specifies the received data reading mode for the
DTLN bits in CFIFOCTR.
If this bit is cleared to 0, the DTLN bits in CFIFOCTR
are cleared when all the received data in the FIFO
buffer that is assigned to the pipe specified by the
CURPOPE bits have been read (in double buffer
mode, the DTLN bit value is cleared when all the
data in a single plane has been read).
If this bit is set to 1, the value in the DTLN bits is
decremented every time the received data is read
from the FIFO buffer that is assigned to the specified
pipe.
0: The DTLN bit is cleared when all of the received
data has been read.
1: The DTLN bit is decremented every time the
received data is read.
Rev. 1.00 Mar. 25, 2008 Page 1156 of 1868
REJ09B0372-0100