SH7205 Datasheet, PDF (254/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
8.1 Features
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels 0 and 1)
User break can be requested as the independent condition on channels 0 and 1.
 Address
Comparison of the 32-bit address is maskable in 1-bit units.
One of the three address buses (F address bus (FAB), M address bus (MAB), and I address
bus (IAB)) can be selected.
 Data
Comparison of the 32-bit data is maskable in 1-bit units.
One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected.
 Bus cycle
Instruction fetch (only when C bus is selected) or data access
 Read/write
 Operand size
Byte, word, and longword
2. In an instruction fetch cycle, it can be selected whether break is set before or after execution of
an instruction.
3. When a break condition is satisfied, a trigger signal can be output from the UBCTRG pin.
Rev. 1.00 Mar. 25, 2008 Page 222 of 1868
REJ09B0372-0100