SH7205 Datasheet, PDF (1378/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Initial
Bit
Bit name
Value
R/W
12
MSK_FILD 1
R/W
11 to 9 
Undefined R
8
MSK_DEMPT 1
R/W
7

Undefined R
6
MSK_ASHFUL 1
R/W
5
MSK_DHFUL 1
R/W
Description
Output Block Last Line Capture Completion Interrupt
Mask
This bit masks a last line capture completion interrupt
for the output block.
0: Enables a last line capture completion interrupt for
the output block.
1: Masks a last line capture completion interrupt for
the output block.
Reserved
The read value is undefined. The write value should
always be 0.
Output Block Input Buffer E Full Interrupt Mask
This bit masks an input buffer E full interrupt for the
output block.
0: Enables an input buffer E full interrupt for the
output block.
1: Masks an input buffer E full interrupt for the output
block.
Reserved
The read value is undefined. The write value should
always be 0.
Blitter Input Buffer A Full Interrupt Mask
This bit masks an input buffer A full interrupt for the
blitter.
0: Enables an input buffer A full interrupt for the
blitter.
1: Masks an input buffer A full interrupt for the blitter.
Blitter Output Buffer C Full Interrupt Mask
This bit masks an output buffer C full interrupt for the
blitter.
0: Enables an output buffer C full interrupt for the
blitter.
1: Masks an output buffer C full interrupt for the
blitter.
Rev. 1.00 Mar. 25, 2008 Page 1346 of 1868
REJ09B0372-0100