SH7205 Datasheet, PDF (620/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary
PWM Mode
Figures 12.58 to 12.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated while
the WRE bit in TWCR is set to 1. In the examples shown in figures 12.58 to 12.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 12.56,
respectively.
TGRA_3
TCDR
Synchronous clearing
Bit WRE = 1
TGRB_3
TCNT_3
(MTU2)
TCNT_4
(MTU2)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 12.58 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 12.56; Bit WRE of TWCR in MTU2 is 1)
Rev. 1.00 Mar. 25, 2008 Page 588 of 1868
REJ09B0372-0100