SH7205 Datasheet, PDF (296/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Figure 10.1 shows a block diagram of the BSC. The BSC consists of an area controller (CSC), an
access controller, and an SDRAM controller (SDRAMC). The CSC controls accessing normal
space in the external address space (see table 10.2). The SDRAMC controls accesses to the
SDRAM space. The access controller controls operations common to both the above-mentioned
normal space and SDRAM space.
CS5 to CS0
RD
RD_WR/WE
WAIT
A25 to A0
WE3/BC3/DQM3
WE2/BC2/DQM2
WE1/BC1/DQM1
WE0/BC0/DQM0
D31 to D0
SDCS1, SDCS0
RAS, CAS
SDWE
CKE
Area controller
(CSC)
CSMODn
CS1WCNTn
CS2WCNTn
Access
controller
SDRAM
controller
(SDRAMC)
CSnCNT
CSnREC
SDCmCNT
SDRFCNT0/1 SDPWDCNT
SDIR0/1
SDDPWDCNT
SDmADR SDSTR
SDmTR
SDCKSCNT
SDmMOD
[Legend]
CSMODn:
CS1WCNTn:
CS2WCNTn:
CSnCNT:
CSnREC:
SDCmCNT:
SDRFCNT0/1:
SDIR0/1:
SDmADR:
SDmTR:
SDmMOD:
SDPWDCNT:
SDDPWDCNT:
SDSTR:
SDCKSCNT:
CSn mode register
CSn wait control register 1
CSn wait control register 2
CSn control register
CSn recovery cycle setting register
SDRAMCm control register
SDRAM refresh control register 0/1
SDRAM initialization register 0/1
SDRAMm address register
SDRAMm timing register
SDRAMm mode register
SDRAM power-down control register
SDRAM deep-power-down control register
SDRAM status register
SDRAM clock stop control signal setting register
Note: n = 0 to 5, m = 0 and 1
Figure 10.1 Block Diagram of BSC
Rev. 1.00 Mar. 25, 2008 Page 264 of 1868
REJ09B0372-0100