SH7205 Datasheet, PDF (266/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
8.4 Operation
8.4.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception handling is described below:
1. The break address is set in the break address register (BAR). The masked address bits are set in
the break address mask register (BAMR). The break data is set in the break data register
(BDR). The masked data bits are set in the break data mask register (BDMR). The bus break
conditions are set in the break bus cycle register (BBR). No user break will be generated if any
one of the three control bit pairs in BBR (C bus cycle/I bus cycle select, instruction fetch/data
access select, and read/write select) is set to 00. The break control settings are made in the bits
of the break control register (BRCR). Make sure to set all registers related to breaks before
setting BBR, and branch after reading from the last written register. The newly written register
values become valid from the instruction at the branch destination.
2. If a the break condition is satisfied, UBC0 (UBC1) sends a user break request to CPU0 (CPU1)
through the INTC, sets the C bus condition match flag (SCMFC) or I bus condition match flag
(SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the width
set by the CKS[1:0] bits. Setting the UBID bit in BBR to 1 enables external monitoring of the
trigger output without requesting user break interrupts.
3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the
user break interrupt has a priority level of 15, it is accepted when the priority level set in the
interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits
are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are
checked, and condition match flags are set if the conditions match. For details on ascertaining
the priority, see section 7, Interrupt Controller (INTC).
4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been
satisfied. Clear the condition match flags during the user break interrupt exception handling
routine. The interrupt occurs again if this operation is not performed.
5. There is a possibility that the break set in channel 0 and the break set in channel 1 occur
around the same time. In this case, there will be only one user break request to the INTC, but
these two break channel match flags may both be set.
6. When selecting the I bus as the break condition, note as follows:
 Whether or not the access the CPU issued on the C bus is issued on the I bus depends on
the setting of the cache. As regard to the I bus operation that depends on cache conditions,
see table 9.8 in section 9, Cache.
 When a break condition is specified for the I bus, only the data access cycle is monitored.
The instruction fetch cycle (including cache update cycle) is not monitored.
Rev. 1.00 Mar. 25, 2008 Page 234 of 1868
REJ09B0372-0100