SH7205 Datasheet, PDF (1528/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 Pin Function Controller (PFC)
(4) Port E Control Register L1 (PECRL1)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PE3MD[3:0]
PE2MD[3:0]
PE1MD[3:0]
PE0MD[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 12 PE3MD[3:0] 0000 R/W PE3 Mode
Select the function of the PE3.
11 to 8 PE2MD[3:0] 0000 R/W PE2 Mode
Select the function of the PE2.
7 to 4 PE1MD[3:0] 0000 R/W PE1 Mode
Select the function of the PE1.
3 to 0 PE0MD[3:0] 0000 R/W PE0 Mode
Select the function of the PE0.
27.2.12 Port F I/O Register L (PFIORL)
PFIORL is a 16-bit readable/writable register that is used to set the pins on port F as inputs or
outputs. The PF4IOR to PF0IOR bits correspond to the PF4 to PF0 pins, respectively. PFIORL is
enabled when the port F pins are functioning as general-purpose inputs/outputs. In other states,
PFIORL is disabled. If a bit in PFIORL is set to 1, the corresponding pin on port F functions as an
output. If it is cleared to 0, the corresponding pin functions as an input.
Bits 15 to 5 in PFIORL are reserved. These bits are always read as 0. The write value should
always be 0.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
PF4 PF3 PF2 PF1 PF0
IOR IOR IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 1496 of 1868
REJ09B0372-0100