SH7205 Datasheet, PDF (1676/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Module
Name Register Name
Abbreviation
2DG
Panel-output vertical timing setting MGR_MIXVTMG
register for output block
(synchronized with VSYNC)
Panel-output mixing vertical valid MGR_MIXVS
area setting register for output
block (synchronized with VSYNC)
Output SYNC setting register for GR_VSDLY
graphics
Video DAC timing setting register VDAC_TMC
PFC
Port A I/O register L
PAIORL
Port A control register L4
PACRL4
Port A control register L3
PACRL3
Port A control register L2
PACRL2
Port A control register L1
PACRL1
Port B I/O register H
PBIORH
Port B I/O register L
PBIORL
Port B control register H2
PBCRH2
Port B control register H1
PBCRH1
Port B control register L4
PBCRL4
Port B control register L3
PBCRL3
Port B control register L2
PBCRL2
Port B control register L1
PBCRL1
Port C I/O register L
PCIORL
Port C control register L3
PCCRL3
Port C control register L2
PCCRL2
Port C control register L1
PCCRL1
Port D I/O register L
PDIORL
Port D control register L1
PDCRL1
Port E I/O register L
PEIORL
Port E control register L4
PECRL4
Port E control register L3
PECRL3
Port E control register L2
PECRL2
Number
of Bits Address
32
H'E80000A8
Access
Size
16, 32
32
H'E80000AC 16, 32
32
H'E80000C4 16, 32
32
H'EA000000 32
16
H'FFFE3802 8, 16
16
H'FFFE380C 8, 16, 32
16
H'FFFE380E 8, 16
16
H'FFFE3810 8, 16, 32
16
H'FFFE3812 8, 16
16
H'FFFE3820 8, 16, 32
16
H'FFFE3822 8, 16
16
H'FFFE3828 8, 16, 32
16
H'FFFE382A 8, 16
16
H'FFFE382C 8, 16, 32
16
H'FFFE382E 8, 16
16
H'FFFE3830 8, 16, 32
16
H'FFFE3832 8, 16
16
H'FFFE3842 8, 16
16
H'FFFE384E 8, 16
16
H'FFFE3850 8, 16, 32
16
H'FFFE3852 8, 16
16
H'FFFE3862 8, 16
16
H'FFFE3872 8, 16
16
H'FFFE3882 8, 16
16
H'FFFE388C 8, 16, 32
16
H'FFFE388E 8, 16
16
H'FFFE3890 8, 16, 32
Rev. 1.00 Mar. 25, 2008 Page 1644 of 1868
REJ09B0372-0100