SH7205 Datasheet, PDF (1126/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.11 Data FIFO Register (FLDTFIFO)
FLDTFIFO is used to read or write the data FIFO area.
In DMA transfer, this register must be specified as the destination or source.
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match
that specified in this register. When changing the read/write direction, FLDTFIFO should be
cleared by setting the AC0CLR bit in FLINTDMACR before use.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFO[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTFO[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
R/W Description
DTFO[31:0] H'xxxxxxxx R/W Data FIFO Area Read/Write Data
In write: Data in this register is written to the data FIFO
area.
In read: Data read from the data FIFO area is stored in
this register.
Rev. 1.00 Mar. 25, 2008 Page 1094 of 1868
REJ09B0372-0100