SH7205 Datasheet, PDF (1890/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Complementary PWM mode .................. 563
Configuration of RCAN-TL1 ............... 1003
Conflict between byte-write and
count-up processes of CMCNT .............. 682
Conflict between word-write and
count-up processes of CMCNT .............. 681
Conflict between write and
compare-match processes of CMCNT.... 680
Conflict error .......................................... 830
Control signal timing ............................ 1768
Control transfer stage transition
interrupt ................................................ 1270
Control transfers when the function
controller function is selected............... 1288
Control transfers when the host
controller function is selected............... 1287
Controller area network (RCAN-TL1) ... 927
CPU .......................................................... 45
Crystal oscillator..................................... 115
Cycle-stealing transfer mode .................. 423
D
D/A converter (DAC) ........................... 1059
D/A converter characteristics ............... 1845
D/A output hold function in software
standby mode........................................ 1065
Data array ....................................... 244, 259
Data format in registers ............................ 50
Data formats in memory ........................... 50
Data transfer instructions.......................... 71
DC characteristics................................. 1753
Definitions of A/D conversion
accuracy................................................ 1054
Delayed branch instructions ..................... 53
Denormalized numbers............................. 96
Determination of DMA channel
priorities.................................................. 445
Device state transition interrupt............ 1268
Rev. 1.00 Mar. 25, 2008 Page 1858 of 1868
REJ09B0372-0100
Direct memory access controller
(DMAC).................................................. 361
Displacement accessing ............................ 55
Divider 1 ................................................. 115
Divider 2 ................................................. 115
DMA activation ...................................... 428
DMA requests ......................................... 440
DMAC activation.................................... 610
DMAC interface ................................... 1027
DMAC timing ....................................... 1785
Dual-processor active state ....................... 89
E
ECC error check.................................... 1112
Effective address calculation .................... 56
Electrical characteristics ....................... 1751
Equation for getting SCBRR value......... 753
Example of time triggered system ........ 1018
Exception handling ................................. 135
Exception handling vector table.............. 139
Exception source generation
immediately after delayed branch
instruction ............................................... 155
Exceptions triggered by instructions....... 151
External trigger input timing................. 1052
F
FIFO buffer........................................... 1276
FLCTL interrupt requests ..................... 1119
FLCTL timing....................................... 1799
Floating-point operation instructions ........ 83
Floating-point ranges ................................ 94
Floating-point registers ............................. 97
Floating-point unit (FPU) ......................... 91
Flow of the user break operation............. 234
Format of double-precision
floating-point number ............................... 92