SH7205 Datasheet, PDF (1010/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
• TXCR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXCR0[15:1]
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
Note: * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as
transmit.
Bit 15 to 1 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel
its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively.
Bit[15:1]: TXCR0
0
1
Description
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition]
Completion of transmit message cancellation (automatically cleared)
Transmission cancellation request made for corresponding mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a ‘1’ to this bit position
has no effect and always read back as a ‘0’.
(3) Transmit Acknowledge Register (TXACK1, TXACK0)
The TXACK1 and TXACK0 are 16-bit read/conditionally-write registers. These registers are used
to signal to the CPU that a mailbox transmission has been successfully made. When a transmission
has succeeded the RCAN-TL1 sets the corresponding bit in the TXACK register. The CPU may
clear a TXACK bit by writing a ‘1’ to the corresponding bit location. Writing a ‘0’ has no effect.
• TXACK1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXACK1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a ‘1’ to clear.
Rev. 1.00 Mar. 25, 2008 Page 978 of 1868
REJ09B0372-0100