SH7205 Datasheet, PDF (1094/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 D/A Converter (DAC)
22.3.2 D/A Control Register (DACR)
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
Bit: 7
6
5
4
3
2
1
0
DAOE1 DAOE0 DAE
-
-
-
-
-
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W R/W -
-
-
-
-
Initial
Bit
Bit Name Value R/W Description
7
DAOE1 0
R/W D/A Output Enable 1
Controls D/A conversion and analog output for channel 1.
0: Analog output of channel 1 (DA1) is disabled
1: D/A conversion of channel 1 is enabled. Analog output
of channel 1 (DA1) is enabled.
6
DAOE0 0
R/W D/A Output Enable 0
Controls D/A conversion and analog output for channel 0.
0: Analog output of channel 0 (DA0) is disabled
1: D/A conversion of channel 0 is enabled. Analog output
of channel 0 (DA0) is enabled.
5
DAE
0
R/W D/A Enable
Used together with the DAOE0 and DAOE1 bits to control
D/A conversion. Output of conversion results is always
controlled by the DAOE0 and DAOE1 bits. For details,
see table 22.3.
0: D/A conversion for channels 0 and 1 is controlled
independently
1: D/A conversion for channels 0 and 1 is controlled
together
4 to 0 
All 1

Reserved
These bits are always read as 1 and cannot be modified.
Rev. 1.00 Mar. 25, 2008 Page 1062 of 1868
REJ09B0372-0100