SH7205 Datasheet, PDF (936/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
1
TDE
1
R(/W)* Transmit Data Empty
Indicates that, when the FIFO is operating for
transmission, the data for transmission in the FIFO data
register (SSIFDR) is transferred to the transmit data
register (SSITDR), the number of data bytes in the
FIFO data register has become less than the transmit
trigger number specified by TTRG[1:0] in the FIFO
control register (SSIFCR), and thus writing of data
transmission to SSIFDR has been enabled.
0: Number of data bytes for transmission in SSIFDR is
greater than the set transmit trigger number.
[Clearing conditions]
• “0” is written to TDE after data of the number of
bytes larger than the set transmit trigger number is
written to SSIFDR.
• The DMAC is activated by transmit data empty (TXI)
interrupt, and data of the number of bytes larger
than the set transmit trigger number is written to
SSIFDR.
1: Number of data bytes for transmission in SSIFDR is
equal to or less than the set transmit trigger number.
[Setting conditions]
• Power-on reset
• Number of bytes of data for transmission in SSIFDR
has become equal to or less than the set transmit
trigger number.*¹
Note: *1 Since SSIFDR is an 8-stage FIFO register,
the amount of data that can be written to it
while TDE = 1 is “8 – set transmit trigger
number” bytes at maximum. Writing more
data will be ignored. The number of data
bytes in SSIFDR is indicated in the DC bits in
SSIFSR.
Rev. 1.00 Mar. 25, 2008 Page 904 of 1868
REJ09B0372-0100