SH7205 Datasheet, PDF (1891/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Format of single-precision
foating-point number ................................ 92
FPU exception sources ........................... 102
FPU-related CPU instructions .................. 85
Full-scale error...................................... 1054
G
General illegal instructions ..................... 152
General registers ....................................... 45
Global base register (GBR) ...................... 47
H
Halt mode ............................................. 1004
H-UDI interrupt ............................ 195, 1597
H-UDI related pin timing...................... 1841
H-UDI reset .......................................... 1597
I
I/O port timing ...................................... 1840
I/O ports................................................ 1507
I²C bus format......................................... 860
I²C bus interface 3 (IIC3) ....................... 841
ID reorder ............................................... 952
IIC3 timing ........................................... 1793
Immediate data ......................................... 54
Immediate data accessing ......................... 54
Immediate data format.............................. 51
Influences on absolute precision........... 1058
Initial values of control registers .............. 49
Initial values of general registers .............. 49
Initial values of system registers............... 49
Instruction features ................................... 52
Instruction format ..................................... 61
Instruction set ........................................... 65
Integer division instructions ................... 153
Internal arbitration for transmission ..... 1008
Interrupt controller (INTC)..................... 159
Interrupt exception handling ................... 150
Interrupt exception vectors and
priorities .................................................. 200
Interrupt priority level............................. 149
Interrupt response time ........................... 209
Interrupt transfers.................................. 1290
IRQ interrupts ......................................... 196
Isochronous transfers ............................ 1292
J
Jump table base register (TBR)................. 47
L
List of DMA transfer conditions ............. 426
Load-store architecture ............................. 52
Local acceptance filter mask (LAFM) .... 943
Logic operation instructions...................... 78
M
Mailbox........................................... 930, 934
Mailbox configuration ............................ 942
Mailbox control....................................... 930
Manual reset............................................ 144
Master receive operation......................... 863
Master transmit operation ....................... 861
Memory-allocated cache ......................... 258
Message control field.............................. 939
Message data fields ................................. 944
Message receive sequence .................... 1022
Message transmission request..... 1008, 1017
Micro processor interface (MPI)............. 930
Module standby mode setting ................. 839
MTU2 functions...................................... 456
MTU2 interrupts ..................................... 608
MTU2 output pin initialization ............... 639
MTU2 timing ........................................ 1786
Multi mode............................................ 1045
Rev. 1.00 Mar. 25, 2008 Page 1859 of 1868
REJ09B0372-0100