SH7205 Datasheet, PDF (1128/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.13 Transfer Control Register (FLTRCR)
Setting the TRSTRT bit to 1 initiates access to flash memory. Access completion can be checked
by the TREND bit. During the transfer (from when the TRSTRT bit is set to 1 until the TREND
bit is set to 1), the processing should not be forcibly ended (by setting the TRSTRT bit to 0).
When reading from flash memory, TREND is set when reading from flash memory have been
finished. However, if there is any read data remaining in the FIFO, the processing should not be
forcibly ended until all data has been read from the FIFO.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
TR TR
END STRT
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 2 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
TREND 0
R/W Processing End Flag Bit
Indicates that the processing performed in the specified
access mode has been completed. The write value
should always be 0.
0
TRSTRT 0
R/W Transfer Start
By setting this bit from 0 to 1 when the TREND bit is 0,
processing in the access mode specified by the access
mode specification bits ACM[1:0] is initiated.
0: Stops transfer
1: Starts transfer
Rev. 1.00 Mar. 25, 2008 Page 1096 of 1868
REJ09B0372-0100