SH7205 Datasheet, PDF (935/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.6 FIFO Status Register (SSIFSR)
SSIFSR consists of status flags indicating the operating status of the FIFO data register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
DC[3:0]
-
-
-
-
-
-
TDE RDF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/(W)* R/(W)*
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Initial
Bit
Bit Name Value R/W Description
31 to 12 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 8 DC[3:0] 0000 R
Number of Data Bytes Stored in SSIFDR
• Transmission
DC[3:0] = H’0 indicates no data for transmission.
DC[3:0] = H’8 indicates that 32 bytes of data for
transmission is stored in SSIFDR.
• Reception
DC[3:0] = H’0 indicates no received data.
DC[3:0] = H’8 indicates that 32 bytes of received
data is stored in SSIFDR.
7 to 2 —
All 0 R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 903 of 1868
REJ09B0372-0100