SH7205 Datasheet, PDF (716/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
Figure 14.1 shows a block diagram of the WDT.
As shown in the figure, the reset output signals from WDT0 and WDT1 upon occurrence of an
overflow are ORed and then output to both CPUs.
Standby cancellation
Interrupt request
WDTOVF
CPU0
CPU1
Internal reset request
Standby
control
WDT0
Interrupt
control
Reset
control
WRCSR0
Divider
Clock selector
Overflow
Clock
WTCSR0
WTCNT0
Standby mode
Peripheral clock
Bus interface
Peripheral bus
WDT1
Interrupt request
Interrupt
control
Reset
control
WRCSR1
Divider
Clock selector
Overflow
Clock
WTCSR1
WTCNT1
Bus interface
[Legend]
WTCSR: Watchdog timer control/status register
WRCSR: Watchdog reset control/status register
WTCNT: Watchdog timer counter
Peripheral bus
Figure 14.1 Block Diagram of WDT
Rev. 1.00 Mar. 25, 2008 Page 684 of 1868
REJ09B0372-0100