SH7205 Datasheet, PDF (1813/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
Ts
T1
(ACT)
T2
T3 T4 T5 T6 T7
(RD) (RD) (RD) (RD) (PRA)
T8
T9
(ACT)
T10
T11 T12 T13 T14 T15
(RD) (RD) (RD) (RD) (PRA)
CKIO
A25 to A0
A12^*
SDCSn
t_AD2 t_AD2
t_AD2 t_AD2 t_AD2 t_AD2 t_AD2 t_AD2 t_AD2
Row C0 (Column C1 C2 C3
Address Address 0)
R1
C4
t_AD2 t_AD2 t_AD2 t_AD2 t_AD2
C5 C6 C7
t_AD2 t_AD2
t_AD2 t_AD2 t_AD2 t_AD2
PRA
command
t_AD2 t_AD2
PRA
command
t_CSD2 t_CSD2 t_CSD2
t_CSD2 t_CSD2 t_CSD2 t_CSD2
t_CSD2
RASL
CASL
t_RASD t_RASD
t_CASD
SDWE
t_RASD t_RASD t_RASD t_RASD
t_CASD
t_CASD
t_WED2 t_WED2
t_RASD t_RASD
t_CASD
t_WED2 t_WED2
CKE
DQMn
t_DQMD
(High)
t_RDS2 t_RDH2
t_RDS2 t_RDH2
t_RDS2 t_RDH2
t_RDS2 t_RDH2
D31 to D0
Note: * An address pin to be connected to pin A10 of SDRAM.
Figure 33.20 SDRAM Space: Bus Timing of Multiple-Read Across Rows
(8 Data Accesses, DLC = 2 (2 Cycles), DRCD = 1 (2 Cycles), DPCG = 1 (2 Cycles))
Rev. 1.00 Mar. 25, 2008 Page 1781 of 1868
REJ09B0372-0100