SH7205 Datasheet, PDF (433/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
16
DREQ 0
15 to 9 
All 0
R/W Description
R/W (Continued)
(c) When a request source other than the software trigger is
selected by the DMA request source select bits (DCTG)
and an edge sense is selected
• Setting condition
This bit is set to 1 when the edge specified in the input
sense mode select bits (STRG) is encountered (when a
DMA request exists).
Once set to 1, regardless of the status of subsequent DMA
request signals, this bit remains set till any of the conditions
for clearing this bit to 0 is met.
• Clearing condition
This bit is cleared to 0 when any of the following conditions
is met:
 Software writes 0 to this bit.
 Operand transfer is started that corresponds to this bit.
Notes: 1. If the selected request source is other than the
software trigger, do not write 1 to this bit. If 1 is
written to this bit, operation is not guaranteed.
2. When the DMA request source select bits (DCTG)
and input sense mode select bits (STRG) of DMA
control register A (DMCNTAn) are set, be sure to
clear the DMA request bit (DREQ) of the set channel
to 0 and then enable DMA transfer (DMST = 1, DEN
= 1).
R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 401 of 1868
REJ09B0372-0100