SH7205 Datasheet, PDF (231/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.5 Interrupt Exception Handling Vector Tables and Priorities
Table 7.8 lists interrupt sources and their vector numbers, vector table address offsets, and
interrupt priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and vector table address offsets. In
interrupt exception handling, the exception service routine start address is fetched from the vector
table indicated by the vector table address. For details of calculation of the vector table address,
see table 6.4 in section 6, Exception Handling.
The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be
set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02,
and 05 to 21 (C0IPR01, C0IPR02, and C0IPR05 to C0IPR21 and C1IPR01, C1IPR02, and
C1IPR05 to C1IPR21). However, if two or more interrupts specified by the same IPR setting
among C0IPR05 to C0IPR21 and C1IPR05 to C1IPR21 occur, the priorities are defined as shown
in the default priorities in table 7.8, and the priorities cannot be changed. A power-on reset assigns
priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. If the
same priority level is assigned to two or more interrupt sources and interrupts from those sources
occur simultaneously, they are processed according to the default priorities indicated in table 7.8.
Rev. 1.00 Mar. 25, 2008 Page 199 of 1868
REJ09B0372-0100