SH7205 Datasheet, PDF (934/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value
R/W Description
1
RIE
0
R/W Receive Interrupt Enable
Enables or disables generation of receive data full
interrupt (RXI) requests when the RDF flag in the FIFO
status register (SSIFSR) is set to 1 while the FIFO is
operating for reception.
0: Receive data full interrupt (RXI) request is disabled
1: Receive data full interrupt (RXI) request is enabled*
Note: * RXI can be cleared by clearing either the RDF
flag (see the description of the RDF bit for
details) or RIE bit.
0
FRST
0
R/W FIFO Data Register Reset
Invalidates the data in the FIFO data register to reset
the FIFO to an empty state.
0: Reset is disabled
1: Reset is enabled
Note: FIFO is reset at a power-on reset.
Rev. 1.00 Mar. 25, 2008 Page 902 of 1868
REJ09B0372-0100