SH7205 Datasheet, PDF (1339/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(2) ATAPI status register (ATAPI_STATUS)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
- SWERR IFERR - DEVTRM DEVINT TOUT ERR NEND ACT
Initial value: -
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/WC0 R/WC0 R R/WC0 R R/WC0 R/WC0 R/WC0 R
Bit
31 to 9
8
Bit Name

SWERR
Initial
Value

0
7
IFERR
0
6

0
5
DEVTRM 0
R/W Description
R
Reserved
R/WC0 This bit is a software error bit. If the bit is set to 1, it
indicates that an attempt was made to access the task
file register when DMA is active. The task register must
not be accessed when DMA is active. The bit is set to
1, for example, if an attempt is made to perform a PIO
transfer during an ultra or multiword DMA transfer. No
error is reported to the outside of the LSI device; the
attempt is merely ignored.
Writing 0 results in the bit being reset.
R/WC0 This bit indicates that an ATAPI interface protocol error
was detected.
• (IDEDREQ = 1) or (IDEIORDY = 0) if ultra DMA
data-in burst was terminated by the host
• IDEIORDY = 0 if ultra DMA data-in burst was
terminated by the device
• IDEIORDY = 0 if ultra DMA data-out burst was
started
• (IDEDREQ = 1) or (IDEIORDY = 0) if ultra DMA
data-out burst was terminated by the host
Writing 0 results in the bit being reset.
R
Reserved
R/WC0 This bit is set to 1 if an ATAPI device exits ultra DMA
mode before the number of transfer bytes specified by
the ATAPI module is reached. Writing 0 results in the
bit being reset.
Rev. 1.00 Mar. 25, 2008 Page 1307 of 1868
REJ09B0372-0100