SH7205 Datasheet, PDF (439/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.14 DMA Transfer End Detection Register (DMEDET)
DMEDET references the DMA transfer end detection status of each channel. Writing 0 to the
DEDET bits is invalid and 1s written to these bits are not retained.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DED DED DED DED DED DED DED DED DED DED DED DED DED DED
ET0 ET1 ET2 ET3 ET4 ET5 ET6 ET7 ET8 ET9 ET10 ET11 ET12 ET13
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 DEDET0 H'0000 R/W When read: DMA Transfer End Condition Detect
to
DEDET13
0: The DMA transfer end condition has not been detected.
1: The DMA transfer end condition was detected.
When written: DMA Interrupt Request Status Clear
0: Invalid
1: Clears the DMA interrupt request status.
These bits enable you to reference the detection status of DMA
transfer end conditions of each channel. Reading this register
does not provide automatic bit clearing. When set to 1, these
bits always retain values unless they are cleared by software.
• Condition for setting these bits to 1
When the DMA transfer end condition is detected, these
bits are set to 1.
• Condition for clearing these bits to 0
These bits are cleared to 0 by writing 1 to them. Write 0 to
the bits not to be cleared. The bits to which 0 was written
retain the values before write operation because they are
not affected by write via software.
To use the DMA transfer end interrupt, write 1 to the DMA
transfer end condition detect bits (DEDET) of the channel
where an interrupt request occurred in the interrupt handler.
When the DMA transfer end condition detect bits (DEDET) are
cleared to 0, the DMA interrupt request status bit (DISTS) is
also cleared to 0.
Rev. 1.00 Mar. 25, 2008 Page 407 of 1868
REJ09B0372-0100