SH7205 Datasheet, PDF (932/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.5 FIFO Control Register (SSIFCR)
SSIFCR is a readable/writable 32-bit register that specifies the data trigger numbers and selects
between transmission and reception for the FIFO data register, and enables or disables FIFO data
reset and interrupt requests.
SSIFCR can always be read or written by the CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
TTRG[1:0]
RTRG[1:0]
-
TIE RIE FRST
0
0
0
0
0
0
R R/W R/W R/W R/W R
0
0
0
R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 8 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
7, 6
TTRG[1:0] 00
R/W Transmit Data Trigger Number
These bits specify the number of transmit data bytes in
the FIFO (transmit trigger number) at which the TDE
flag in the FIFO status register (SSIFSR) is set while
the FIFO is operating for transmission.
The TDE flag is set to 1 when the number of transmit
data bytes in the FIFO data register (SSIFDR) has
become equal to or less than the set trigger number
shown below.
00: 7 (1)*
01: 6 (2)*
10: 4 (4)*
11: 2 (6)*
Note: The values in parenthesis are the number of
empty stages in SSIFDR at which the TDE flag is
set.
Rev. 1.00 Mar. 25, 2008 Page 900 of 1868
REJ09B0372-0100