SH7205 Datasheet, PDF (413/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.5 _{DMA Reload Destination Address Register (DMRDADRn)}
DMRDADRn is a register used to set an address to be reloaded to the DMA current destination
address register (DMCDADRn).
To enable the reload function, set the DMA destination address reload function enable bit
(DRLOD) in DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current
destination address register (DMCDADRn) and DMA reload destination address register
(DMRDADRn).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDA[31:16]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDA[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
RDA[31:0]
Initial
Value
R/W
Undefined R/W
Description
Holds reload destination address bits A31 to A0.
Note:
Set this register so that DMA transfer is performed for the following selected transfer data
sizes within the correctly arranged address boundaries:
• When the transfer data size is set to 16 bits (SZSEL = 001): (bit 0) = 0
• When the transfer data size is set to 32 bits (SZSEL = 010): (bit 1, bit 0) = (0, 0)
Rev. 1.00 Mar. 25, 2008 Page 381 of 1868
REJ09B0372-0100