SH7205 Datasheet, PDF (445/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.18 DMA Two-Dimensional Addressing Block Setting Register (DM2DBLKm)
DM2DBLKm is a register used to set the number of blocks per line in two-dimensional
addressing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
DBN[23:16]
Initial value: 0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DBN[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 24 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
23 to 0 DBN
[23:0]
Undefined R/W DMA Block Count
These bits are used to set the number of blocks in one line.
00000000_00000000_00000000: 1 block
:
11111111_11111111_11111111: 16777216 blocks
Rev. 1.00 Mar. 25, 2008 Page 413 of 1868
REJ09B0372-0100