SH7205 Datasheet, PDF (1276/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.14 Information Cleared by this Module by Setting ACLRM = 1
Information Cleared by ACLRM Bit
No. Manipulation
Cases in which Clearing the Information
is Necessary
1 All the contents in the FIFO buffer assigned 
to the pertinent pipe (all the contents in two
FIFO buffer planes in double buffer mode)
2 The interval count value when the pertinent When the interval count value is to be reset
pipe is for isochronous transfer
3 Values of the internal flags related to the
BFRE bit
When the BFRE setting is modified
4 FIFO buffer toggle control
When the DBLB setting is modified
5 Values of the internal flags related to the
transaction count
When the transaction count function is
forcibly terminated
Table 24.15 Operation of This Module depending on PID Setting (when Host Controller
Function is Selected)
PID Bits
Transfer Type
(TYPE Bits)
Transfer Direction
(DIR Bit)
Operation of This Module
00 (NAK)
Operation does not Operation does not Does not issue tokens.
depend on the
depend on the
setting.
setting.
01 (BUF)
Bulk or interrupt
Operation does not Issues tokens while UACT is 1 and the
depend on the
FIFO buffer corresponding to the
setting.
pertinent pipe is ready for transmission
and reception.
Does not issue tokens while UACT is 0
or the FIFO buffer corresponding to the
pertinent pipe is not ready for
transmission or reception.
Isochronous
Operation does not Issues tokens irrespective of the status
depend on the
of the FIFO buffer corresponding to the
setting.
pertinent pipe.
10 (STALL) or Operation does not Operation does not Does not issue tokens.
11 (STALL) depend on the
depend on the
setting.
setting.
Rev. 1.00 Mar. 25, 2008 Page 1244 of 1868
REJ09B0372-0100