SH7205 Datasheet, PDF (73/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Classification Symbol
I/O
AT attachment IDED15 to
I/O
packet interface IDED0
(ATAPI)
IDEA2 to IDEA0 O
IODACK#
O
IODREQ
O
IDECS#1,
O
IDECS#0
IDEIOWR#
O
IDEIORD#
O
IDEIORDY
I
IDEINT
I
IDERST#
O
DIRECTION O
2D engine (2DG) R, G, B
O
REXT
I
CBU
O
VIHSYNC
I
VIVSYNC
I
VICLK
I
VIDATA7 to I
VIDATA0
VICLKENB
I
CSYNC
O
DCLKIN
I
Name
Data bus
Function
Bidirectional data bus
Address bus
DMA
acknowledge
DMA request
Chip select
Address bus
Primary channel DMA acknowledge
Primary channel DMA request
Primary channel chip select
Write
Primary channel disk write
Read
Primary channel disk read
Ready
Primary channel ready signal
Interrupt request Primary channel interrupt request
Reset
Primary channel ATAPI device reset
Direction
External level shifter direction signal
RGB output
RGB analog output pins
External
External reference input pin for D/A
reference input converter
External
capacitance
output
External capacitance output pin for
D/A converter
HSYNC signal HSYNC signal input
VSYNC signal VSYNC signal input
Pixel clock
Pixel clock input
Image data
Image data input
Clock enable
CSYNC signal
Dot clock
Indicates that pixel data is valid
Composite sync signal after graphic
processing
Dot clock input
Rev. 1.00 Mar. 25, 2008 Page 41 of 1868
REJ09B0372-0100