SH7205 Datasheet, PDF (157/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
9, 8
STC[1:0] 01/10* R/W Frequency Multiplication Rate of PLL Circuit
• Clock modes 0, 1, and 2
00: Reserved (setting prohibited)
01: × 12 (initial value)
10: × 16
11: Reserved (setting prohibited)
• Clock mode 3
00: Reserved (setting prohibited)
01: × 12
10: × 16 (initial value)
11: Reserved (setting prohibited)
7, 6

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4
IFC[1:0] 10/01* R/W Division Ratio of CPU0 Internal Clock Frequency (I₀φ)
Specify the division ratio for the CPU0 internal clock, which
is used in division of the output frequency of the PLL circuit.
• Clock modes 0, 1, and 2
00: × 1
01: × 1/2
10: × 1/3 (initial value)
11: Reserved (setting prohibited)
• Clock mode 3
00: × 1
01: × 1/2 (initial value)
10: × 1/3
11: Reserved (setting prohibited)
3

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 125 of 1868
REJ09B0372-0100