SH7205 Datasheet, PDF (996/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
(4) Interrupt Request Register (IRR)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the
various interrupt sources.
• IRR (Address = H'008)
Bit: 15 14 13 12 11 10 9
IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
8
IRR8
0
R
7
IRR7
0
R/W
6
IRR6
0
R/W
5
IRR5
0
R/W
4
IRR4
0
R/W
3
IRR3
0
R/W
2
IRR2
0
R
1
IRR1
0
R
0
IRR0
1
R/W
Bit 15 — Timer Compare Match Interrupt 1 (IRR15): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the
TCMR1 matches to Cycle Time (TCMR1 = CYCTR), this bit is set.
Bit 15: IRR15
0
1
Description
Timer Compare Match has not occurred to the TCMR1 (Initial value)
[Clearing condition] Writing 1
Timer Compare Match has occurred to the TCMR1
[Setting condition] TCMR1 matches to Cycle Time (TCMR1 = CYCTR)
Bit 14 — Timer Compare Match Interrupt 0 (IRR14): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 0 (TCMR0). When the value set in the
TCMR0 matches to Local Time (TCMR0 = TCNTR), this bit is set.
Bit 14: IRR14
0
1
Description
Timer Compare Match has not occurred to the TCMR0 (Initial value)
[Clearing condition] Writing 1
Timer Compare Match has occurred to the TCMR0
[Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR)
Bit 13 - Timer Overrun Interrupt/Next_is_Gap Reception Interrupt/Message Error
Interrupt (IRR13): This interrupt assumes a different meaning depending on the RCAN-TL1
mode. It indicates that:
 The Timer (TCNTR) has overrun when RCAN-TL1 is working in event-trigger mode
(including test modes)
Rev. 1.00 Mar. 25, 2008 Page 964 of 1868
REJ09B0372-0100