SH7205 Datasheet, PDF (228/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.4.4 IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. For an explanation of how to configure pins
IRQ7 to IRQ0, see section 27, Pin Function Controller (PFC). For IRQ7 to IRQ0, low-level,
falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the
IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control registers 1
(C0ICR1 and C1ICR1). The priority level can be set individually in a range from 0 to 15 for each
pin by interrupt priority registers 01 and 02 (C0IPR01, C0IPR02, C1IPR01, and C1IPR02). The
CPU that should accept the IRQ interrupts can be selected by the IRQ interrupt enable control
registers (C0IRQER and C1IRQER).
When low-level detection is used for IRQ interrupts, an interrupt request signal is sent to the INTC
while the IRQ7 to IRQ0 pins are low. An interrupt request signal is no longer sent to the INTC
when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked
by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request registers
(C0IRQRR and C1IRQRR).
When edge-detection is used for IRQ interrupts, an interrupt request is detected due to change of
the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ
interrupt request detection is retained until that interrupt request is accepted. Whether IRQ
interrupt requests have been detected or not can be checked by reading IRQ7F to IRQ0F in
C0IRQRR and C1IRQRR. The result of IRQ interrupt request detection can be cleared by reading
1 from these bits and then writing 0 to them.
The IRQ interrupt exception handling sets the I3 to I0 bits in the SR to the priority level of the
accepted IRQ interrupt.
When returning from the IRQ interrupt exception service routine, execute the RTE instruction
after using C0IRQRR and C1IRQRR to ensure that the interrupt request has been cleared, so as
not to accidentally receive the interrupt request again.
Rev. 1.00 Mar. 25, 2008 Page 196 of 1868
REJ09B0372-0100