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SH7205 Datasheet, PDF (106/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series | |||
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Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) â
1

Yes
zero extension â Rn
1000dddddddddddd
MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp à 2 + Rm) â
1

Yes
zero extension â Rn
1001dddddddddddd
NOTT
0000000001101000 ~T â T
1
Ope-
Yes
ration
result
PREF @Rn
0000nnnn10000011 (Rn) â operand cache
1

Yes Yes
SWAP.B Rm,Rn
0110nnnnmmmm1000 Rm â swap lower 2 bytes â 1
Rn
 Yes Yes Yes
SWAP.W Rm,Rn
0110nnnnmmmm1001 Rm â swap upper and lower 1
words â Rn
 Yes Yes Yes
XTRCT Rm,Rn
0010nnnnmmmm1101 Middle 32 bits of Rm:Rn â Rn 1
 Yes Yes Yes
Rev. 1.00 Mar. 25, 2008 Page 74 of 1868
REJ09B0372-0100
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