SH7205 Datasheet, PDF (324/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT)
SDDPWDCNT controls transition to and recovery from deep-power-down mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DDPD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit
31 to 1
Initial
Bit Name Value

All 0
0
DDPD 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W SDRAM Common Deep-Power-Down Enable
This bit controls transition to and recovery from deep-
power-down mode for all channels simultaneously. Setting
DDPD to 1 causes all SDRAM channels to transfer to
deep-power-down mode. Clearing DDPD to 0 causes all
SDRAM channels to recover from deep-power-down
mode. If an auto-refresh is in progress, the transition to
deep-power-down mode is delayed until the auto-refresh
completes.
0: Deep-power-down disabled
1: Deep-power-down enabled
Rev. 1.00 Mar. 25, 2008 Page 292 of 1868
REJ09B0372-0100