SH7205 Datasheet, PDF (1333/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
25.3 Register Description
The following register set is allocated in the on-chip peripheral module space of this LSI device.
25.3.1 ATAPI Interface Registers
Table 25.2 ATA Task File Register Map
(These resisters are allocated to the ATAPI or ATA device, but not to this module.)
Address
Read Register Write Register
Pin Address
(IDECS[1:0]#,
IDEA[2:0])
H: High Level
L: Low
Level@3.3V I/O
Access Size*¹
(Available Bit Register
Size)
Location
H'FFFECC00 Data
Data
HL-LLL/HH-XXX 32 (16)*²
(X: Don't care)
Drive
H'FFFECC04 Error
Function
HL-LLH
32 (8)*³
Drive
H'FFFECC08 Sector count Sector count HL-LHL
32 (8)*³
Drive
H'FFFECC0C Sector number Sector number HL-LHH
32 (8)*³
Drive
H'FFFECC10 Cylinder low Cylinder low
HL-HLL
32 (8)*³
Drive
H'FFFECC14 Cylinder high Cylinder high HL-HLH
32 (8)*³
Drive
H'FFFECC18 Device/head Device/head
HL-HHL
32 (8)*³
Drive
H'FFFECC1C Status
Command
HL-HHH
32 (8)*³
Drive
H'FFFECC38 Alternate status Device control LH-HHL
32 (8)*³
Drive
Notes: 1. The CPU must access these registers in longword (32-bit) units. Byte and word
accesses are prohibited.
2. Bits 15 to 0 of the data bus are used.
3. Bits 7 to 0 of the data bus are used.
Rev. 1.00 Mar. 25, 2008 Page 1301 of 1868
REJ09B0372-0100