SH7205 Datasheet, PDF (212/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.10 Inter-Processor Interrupt Control Registers 15 to 08 (C0IPCR15 to C0IPCR08,
C1IPCR15 to C1IPCR08)
C0IPCR15 to C0IPCR08 and C1IPCR15 to C1IPCR08 are 16-bit registers that generate inter-
processor interrupts when 1 is written to any of the CI bits. Each CI bit remains 1 until the target
processor accepts interrupt processing, and the bit is cleared to 0 upon completion of the
acceptance.
An inter-processor interrupt request made from CPU0 is set in one of C1IPCR15 to C1IPCR08.
An inter-processor interrupt request made from CPU1 to CPU0 is set in one of C0IPCR15 to
C0IPCR08.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CI
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Initial
Bit
Bit Name Value R/W Description
15 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
CI
0
R/W Inter-processor Interrupt Request
0: Inter-processor interrupt request is not set.
1: Inter-processor interrupt request is set.
Note: Although 0 can be written to the CI bit, an inter-processor interrupt request is held pending
internally, and cannot be cleared.
Rev. 1.00 Mar. 25, 2008 Page 180 of 1868
REJ09B0372-0100