SH7205 Datasheet, PDF (1490/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.4.4 Output Operations
(1) Summary of Operations between the Output Block and External Memory
The following is a summary of operations between the output block and external memory.
1. The output block negates the DMA request signal and accepts a DMA transfer from the
external memory.
2. The SE buffers (SE1, SE2), alternately buffer the data received through the DMA transfer.
3. Triggered by the VSYNC signal, the data undergoes various processings and then output to the
panel unit.
4. Steps 1 to 3 are repeated until all data processing is completed.
VSYNC
The OUTEN bits in the
GR_MIXPLY register
DMA transfer
SE1 match (SEHF_STAT (0))
SE2 match (SEHF_STAT (1))
Graphic reproduction
DMA1 request
E1
E2
E1
E2
E1
E2
E1
E2
E1
E2
E1
Figure 26.51 Summary of Operations between Output Block and External Memory
(2) Pixel Format Conversion in Output Block
For the output block, either αRGB444 or αRGB555 can be set as the pixel format. The output
block uses 6 bits for each color in blending involving the moving pictures. For this reason, a given
format is converted into a standard format: α (4 bits) + RGB (6 bits each) for a total of 22 bits.
The formula below shows rules for the conversion of a given format to the standard format:
Rev. 1.00 Mar. 25, 2008 Page 1458 of 1868
REJ09B0372-0100