SH7205 Datasheet, PDF (1597/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
0
RRAMKP0 0
R/W RRAM Storage Area 0 (page 0* of on-chip RAM for data
retention)
0: The contents of the corresponding on-chip RAM area are
not retained in deep standby mode.
1: The contents of the corresponding on-chip RAM area are
retained in deep standby mode.
Note: * For the addresses of each page, see section 29, On-Chip RAM.
30.2.24 Deep Standby Control Register (DSCTR)
DSCTR is an 8-bit readable/writable register that selects whether to retain the states on the
external bus control pins when returning from deep standby mode and specifies the method of how
the LSI starts up on recovery.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
CS0 RAM
KEEPE BOOT
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
Bit
7
6
5 to 0
Initial
Bit Name Value
CS0KEEPE 0
RAMBOOT 0

All 0
R/W Description
R/W Retention of External Bus Control Pin State
0: The state of the external bus control pins is not retained
when returning from deep standby mode.
1: The state of the external bus control pins is retained when
returning from deep standby mode.
R/W Method of Recovery from Deep Standby Mode
In the power-on reset exception handling executed when
deep standby mode is canceled by the MRES, NMI, or IRQ,
the program counter (PC) and the stack pointer (SP) are
retrieved from the following addresses, respectively.
0: Addresses H'00000000 and H'00000004
1: Addresses H'FF800000 and H'FF800004
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1565 of 1868
REJ09B0372-0100