SH7205 Datasheet, PDF (229/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.4.5 PINT Interrupts
PINT interrupts are input from pins PINT7 to PINT0. For an explanation of how to configure pins
PINT7 to PINT0, see section 27, Pin Function Controller (PFC). Input of the interrupt requests is
enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable registers
(C0PINTER and C1PINTER). For PINT7 to PINT0, low-level or high-level detection can be
selected individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt
control registers 2 (C0ICR2 and C1ICR2). A single priority level in a range from 0 to 15 can be
set for all PINT7 to PINT0 interrupts by bits 15 to 12 in interrupt priority registers 05 (C0IPR05
and C1IPR05).
When low-level detection is used for the PINT7 to PINT0 interrupts, an interrupt request signal is
sent to the INTC while the PINT7 to PINT0 pins are low. An interrupt request signal is no longer
sent to the INTC when the PINT7 to PINT0 pins are driven high. The status of the interrupt
requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the
PINT interrupt request registers (C0PIRR and C1PIRR). The above description also applies to a
case in which high-level detection is used, except for the polarity being reversed. The PINT
interrupt exception handling sets the I3 to I0 bits in the SR to the priority level of the PINT
interrupt.
When returning from the PINT interrupt exception service routine, execute the RTE instruction
after using C0PIRR and C1PIRR to ensure that the interrupt request has been cleared, so as not to
accidentally receive the interrupt request again.
Rev. 1.00 Mar. 25, 2008 Page 197 of 1868
REJ09B0372-0100