SH7205 Datasheet, PDF (161/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
6. To change the WTCNT0 value after executing a frequency changing instruction, read
WTCNT0 to make sure that it holds a value of H'00.
7. Since the CPU1 stays in the sleep state after execution of the frequency changing instruction,
wake it up by using an interrupt or other means before using it.
Figure 5.2 shows a sample procedure for changing the multiplication rate of the PLL circuit from
×12 to ×16 in clock mode 0.
Reset
Access FRQCR1 from CPU1 to change
the setting from H'0020 to H'0000.
Read FRQCR1 3 times from CPU1.
Execute the sleep instruction from CPU1 to
place CPU1 in the sleep state.
Read C1MSR from CPU0 to make sure that
CPU1 is in the sleep state.
Read the register until C1MSR is set to H'01.
Configure WDT0.
• Stop WDT0.
(Set the TME bit of WTCSR0 to B'0.)
• Set the division ratio of the WDT0 count clock.
(Set the CKS bit of WTCSR0 to B'110.)
• Set the initial value of WDT0 counter.
(Set the WTCNT0 to H'00.)
Access FRQCR0 from CPU0 to change
the setting from H'0124 to H'0205.
The LSI stops operation temporarily
and counting up by WDT0 starts.
Supply of the set clock starts on overflow of
WDT0 and CPU0 starts operation.
Since CPU1 is still in the sleep state, wake
it up by interrupt or other means before use.
Figure 5.2 Sample Procedure for Changing the Multiplication Rate of the PLL Circuit
from ×12 to ×16
Rev. 1.00 Mar. 25, 2008 Page 129 of 1868
REJ09B0372-0100