SH7205 Datasheet, PDF(171/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (171/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 6 Exception Handling

6.1.3 Exception Handling Vector Table

Before exception handling begins running, the exception handling vector table must be set in

memory. The exception handling vector table stores the start addresses of exception service

routines. (The reset exception handling table holds the initial values of PC and SP.)

All exception sources are given different vector numbers and vector table address offsets, from

which the vector table addresses are calculated. During exception handling, the start addresses of

the exception service routines are fetched from the exception handling vector table, which is

indicated by this vector table address.

Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector

table addresses are calculated.

Table 6.3 Exception Handling Vector Table

Exception Sources

Power-on reset PC

SP

Manual reset

PC

SP

General illegal instruction

(Reserved by system)

Slot illegal instruction

(Reserved by system)

CPU address error

(Reserved by system)

Interrupts

NMI

User break

FPU exception

H-UDI

Bank overflow

Bank underflow

Integer division exception

(division by zero)

Vector

Receipt CPU

Numbers Vector Table Address Offset Selection*1

0

H'00000000 to H'00000003 Both CPUs

1

H'00000004 to H'00000007 Both CPUs

2

H'00000008 to H'0000000B Both CPUs

3

H'0000000C to H'0000000F Both CPUs

4

H'00000010 to H'00000013 Each CPU

5

H'00000014 to H'00000017 ï£§

6

H'00000018 to H'0000001B Each CPU

7

H'0000001C to H'0000001F ï£§

8

H'00000020 to H'00000023 ï£§

9

H'00000024 to H'00000027 Each CPU

10

H'00000028 to H'0000002B ï£§

11

H'0000002C to H'0000002F User selection A

12

H'00000030 to H'00000033 Each CPU

13

H'00000034 to H'00000037 Each CPU

14

H'00000038 to H'0000003B User selection A

15

H'0000003C to H'0000003F Each CPU

16

H'00000040 to H'00000043 Each CPU

17

H'00000044 to H'00000047 Each CPU

Rev. 1.00 Mar. 25, 2008 Page 139 of 1868

REJ09B0372-0100

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