SH7205 Datasheet, PDF (137/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Multi-Core Processor
Section 4 Multi-Core Processor
This LSI includes two SH2A CPUs (CPU0 and CPU1). Dual CPUs provide this LSI with strong
levels of performance (through distribution of load) and functionality (through distribution of
functions) in processing, which cannot be achieved by a single CPU.
4.1 Features
• Synchronization control between CPUs
Inter-processor interrupts support control of synchronization between the two CPUs (see
section 7, Interrupt Controller (INTC)).
• Exclusive control for shared resources
Semaphore control registers support exclusive control for shared resources.
• Floating-point unit (FPU), cache memory, and high-speed on-chip RAM are provided for each
CPU
Each CPU has its own FPU, cache memory, and high-speed on-chip RAM.
The high-speed on-chip RAM can be configured as shared RAM space or as CPU-specific
RAM space by enabling or disabling access from the other CPU (see section 29, On-Chip
RAM).
• Power-down modes (see section 30, Power-Down Modes)
To reduce power consumption, this LSI can move between dual-processor mode, where both
CPUs are operating, single-processor mode, where one CPU is in the sleep state, and dual-
sleep mode, where both CPUs are in the sleep state. By making transitions between these
modes in accordance with the load, power consumption can be reduced while high
performance is maintained.
• Multiple-internal-bus structure (see section 1, Overview)
To prevent deterioration in performance due to both CPUs and the DMAC not being able to
get bus mastership, multiple (four) internal buses are provided.
Rev. 1.00 Mar. 25, 2008 Page 105 of 1868
REJ09B0372-0100