SH7205 Datasheet, PDF (1569/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 29 On-Chip RAM
Section 29 On-Chip RAM
This LSI has an on-chip high-speed RAM, which achieves fast access, and an on-chip RAM for
data retention, which can retain data even in deep standby mode. These memory units can store
instructions or data.
The memory operation and writing operation of the on-chip high-speed RAM can be enabled or
disabled through the RAM enable bits and RAM write enable bits.
For the on-chip RAM for data retention, it is possible to specify whether to retain data in deep
standby mode on a page-by-page basis.
29.1 Features
• Pages
On-chip high-speed RAM0 consists of four pages (pages 0, 1, 2, and 3) and on-chip high-speed
RAM1 consists of two pages (pages 0 and 1) and each of these pages has a size of 16 Kbytes.
The on-chip RAM for data retention consists of four pages and each of these pages has a size
of 4 Kbytes.
• Memory map
The on-chip high-speed RAMs are allocated in the address space shown in tables 29.1 and
29.2. The on-chip RAM for data retention is allocated in the address space shown in table 29.3.
When a common area for CPU0 and CPU1 is placed on the on-chip high-speed RAMs and the
area is exclusively accessed by the TAS.B instruction, the on-chip high-speed RAMs should be
accessed through the address space shown in table 29.2.
Rev. 1.00 Mar. 25, 2008 Page 1537 of 1868
REJ09B0372-0100