SH7205 Datasheet, PDF (1609/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
4. Set the STBY and DEEP bits in STBCR1 to 1.
5. Clear the flag in DSFR and then read DSFR.
6. Set to disable an interrupt to CPU1 and confirm that the SLEEP bit in C1MSR is 1, and then
execute the SLEEP instruction by CPU0.
Set the RRAMKP bit
in RRAMKP as required.
Transfer data that needs to be
retained to the corresponding
area.
Set the corresponding bit
in DSSSR as required.
Set the registers of the
INTC as required.
Perform read/write to the same
arbitrary address in each
retention page of the on-chip
RAM (for data retention).
Set the STBY and DEEP bits
in STBCR1 to 1.
Read STBCR1
Clear the flag of DSFR
and read DSFR.
Set to disable an interrupt
to CPU 1.
Confirm that the SLEEP bit
in C1MSR is 1, and then CPU0
executes the SLEEP instruction.
Transition to deep standby mode
Figure 30.3 Flowchart of Transition to Deep Standby Mode
Rev. 1.00 Mar. 25, 2008 Page 1577 of 1868
REJ09B0372-0100