SH7205 Datasheet, PDF (288/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
9.3.5 Write-Back Buffer (Only for Operand Cache)
When the U bit of the entry to be replaced in write-back mode is 1, it must be written back to the
external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the cache completes to fetch the new entry, the write-back buffer writes
the entry back to external memory. During the write-back cycles, the cache can be accessed.
The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure
9.3 shows the configuration of the write-back buffer.
A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
A (31 to 4):
Physical address written to external memory (upper three bits are 0)
Longword 0 to 3: One line of cache data to be written to external memory
Figure 9.3 Write-Back Buffer Configuration
Table 9.8 summarizes the above operations in sections 9.3.2 to 9.3.5.
Rev. 1.00 Mar. 25, 2008 Page 256 of 1868
REJ09B0372-0100