SH7205 Datasheet, PDF (227/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.4 Interrupt Sources
There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip
peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the
highest. When set to level 0, that interrupt is masked at all times.
7.4.1 NMI Interrupts
An NMI interrupt has a priority level of 16 and is accepted at all times. NMI pin inputs are edge-
detected, and the NMI sense select bits (NMIS) in interrupt control registers 0 (C0ICR0 and
C1ICR0) select whether interrupt requests are detected on the rising edge or falling edge. The
CPU that should accept the NMI interrupts can be selected by the interrupt enable control registers
(C0INTER and C1INTER).
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the
interrupt mask bits (I3 to I0) in the status register (SR) to level 15.
7.4.2 User Break Interrupts
A user break interrupt has a priority level of 15, and occurs when a break condition set in the user
break controller (UBC) is satisfied. User break interrupt requests are edge-detected and retained
until they are accepted. The user break exception handling sets the I3 to I0 bits in the SR to level
15. For user break interrupts, see section 8, User Break Controller (UBC).
7.4.3 H-UDI Interrupts
A user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial input
of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained until
they are accepted. The CPU that should accept the H-UDI interrupts can be selected by the
interrupt enable control registers (C0INTER and C1INTER). The H-UDI exception handling sets
the I3 to I0 bits in the SR to level 15. For H-UDI interrupts, see section 31, User Debugging
Interface (H-UDI).
Rev. 1.00 Mar. 25, 2008 Page 195 of 1868
REJ09B0372-0100